An FPGA Implementation of a Bistable Ring PUF

Abstract: Physical Unclonable Functions have a great potential in the field of secure data transmission. Out of the many PUF designs, the bistable ring (BR) PUF has proven to be strong in terms of the secure data transmission. In this project a 32-bit bistable ring PUF is implemented on FPGA together with a pseudo random number generator for providing the challenges, an UART interface for reading the responses and an FSM for controlling the process. The design is described in VHDL, is synthesized on FPGA and its functionality is tested by displaying the challenge-response pairs in a computer terminal.